• DocumentCode
    3109993
  • Title

    The architecture design for a terabit IP switch router

  • Author

    Yang, Jie ; Uzan, N. ; Papavassiliou, Symeon

  • Author_Institution
    Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    358
  • Lastpage
    362
  • Abstract
    We propose an architecture for scalable, high capacity IP switch routers in which we apply fixed-length packet switching technology to support high speed IP forwarding. The proposed IP switch router consists of routing controllers, routing modules and a switch plane. The architectures of routing modules and switch plane whose aggregate capacity can be as large as ten terabit are proposed. The throughput of the IP switch router is guaranteed by a fixed-length packet switch plane which is able to emulate the ideal output queueing (OQ) switch in terms of throughput and average internal queueing delay. The performance of the switch plane is presented and the link list operations of routing modules are investigated
  • Keywords
    Internet; controllers; delays; distributed processing; packet switching; quality of service; queueing theory; telecommunication network routing; transport protocols; Internet; architecture design; average internal queueing delay; fixed-length packet switching; high capacity IP switch routers; high speed IP forwarding; performance; routing controllers; routing modules; scalable architecture; switch plane; terabit IP switch router; throughput; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Switching and Routing, 2001 IEEE Workshop on
  • Conference_Location
    Dallas, TX
  • Print_ISBN
    0-7803-6711-1
  • Type

    conf

  • DOI
    10.1109/HPSR.2001.923661
  • Filename
    923661