Optimal use of timing resources: a crucial step in test program generation

A modified timing set priority strategy and a lookahead register-replacement algorithm is presented for automatic test program generation. These methodologies are introduced to satisfy the testing requirements in complex VLSI chips, and are made possible by the increasing timing flexibility of modern ATE (automatic test equipment). It is shown that by applying optimization algorithms in allocating timing resources and a published timing set determination algorithm, that testing capability of modern ATE can be greatly extended. Further enhancements to these approaches are contingent on further improvements from ATE manufacturers in the number and flexibility of timing resources. However, the development of test programs will be greatly aided by this enhanced hardware