• DocumentCode
    3110147
  • Title

    Dynamic techniques for yield enhancement of field programmable logic arrays

  • Author

    Demjanenko, Mlichael ; Upadhyaya, Shambhu J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
  • fYear
    1988
  • fDate
    12-14 Sep 1988
  • Firstpage
    485
  • Lastpage
    491
  • Abstract
    Two techniques are presented to increase the effective yield of field programmable logic arrays (FPLAs). In the first technique, a reconfiguration scheme is proposed to dynamically alter the product-term allocation of the mask PLA onto the product lines of the raw FPLA once a type-two fault is diagnosed. This technique does not require any extra product lines to obtain a usable destination FPLA. The second technique utilizes the often unused product lines within the FPLA. It is shown that once an error is detected during the programming procedure, a product line can always be desensitized from the rest of the FPLA. The intended product term is then simply reprogrammed onto one of the extra product lines
  • Keywords
    VLSI; integrated circuit testing; integrated logic circuits; logic arrays; logic testing; production testing; IC testing; diagnosis; fault location; field programmable logic arrays; mask PLA; product lines; reconfiguration; yield enhancement; Circuit faults; Computer aided manufacturing; Costs; Fuses; Hardware; Programmable logic arrays; Reconfigurable logic; Redundancy; Semiconductor device measurement; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1988. Proceedings. New Frontiers in Testing, International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-8186-0870-6
  • Type

    conf

  • DOI
    10.1109/TEST.1988.207760
  • Filename
    207760