High performance vedic BCD multiplier and modified binary to BCD converter

Decimal data processing applications have grown exponentially in recent years and the IEEE 754-2008 standard for floating point arithmetic has already dictated the importance of decimal arithmetic. In Computer Science where more accurate data processing is demanded, decimal arithmetic plays an important role to support the most accurate data processing at the level of financial and scientific calculations where errors aren´t acceptable at all. In most hardware approaches that have been proposed for decimal arithmetic, the implementation of multiplication is very expensive in terms of occupied resources and path delay. In this paper we proposed single and multi-digit BCD-8421 multiplier using the Vedic mathematics, and modified Binary to BCD Converter. We have also implemented our proposed algorithms for the Xillinx FPGA device, vertex-4 xc4vfx12. Synthesized results depict that the Vedic BCD multiplier is faster; more than 2 times and occupies 4 times less hardware slices.