Title :
A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator
Author :
Hirose, Fumiyasu ; Takayama, Koichiro ; Kawato, Nobuaki
Author_Institution :
Fujitsu Lab. Ltd., Japan
Abstract :
A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP)
Keywords :
automatic testing; combinatorial circuits; digital simulation; integrated logic circuits; logic testing; combinational logic circuits; test generation; test patterns; ultrahigh-speed logic simulator; Automatic testing; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Combinational circuits; Computational modeling; Logic testing; Parallel processing; Registers;
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-0870-6
DOI :
10.1109/TEST.1988.207786
