Test vector reordering to reduce peak temperature during testing

With rapid progress in VLSI technology, temperature during testing has become a big issue. As increase in temperature during testing causes permanent or temporal damage of the chip, reduction in peak temperature of the chip becomes necessary. Temperature depends on both heat generation caused by power consumption and heat dissipation among neighboring blocks in the circuit under test (CUT). Heat generation can be reduced by reordering test vectors in a way such that transitions caused by them get reduced. However, heat dissipation depends on thermal gradient. To reduce the heat dissipation and also the peak temperature, the test vectors can be reordered to bring a reduction in the transitions of a block and its neighbors. In this paper we have proposed a particle swarm optimization (PSO) based technique which reorders test vectors in a way such that peak temperature is reduced. Experimental results of our proposed approach on ISCAS´89 benchmark circuits show an enriched reduction in peak temperature with nominal CPU time.