Testability features of a 32 kbps ADPCM transcoder

Author

Bonet, Luis A.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1988

fDate

12-14 Sep 1988

Firstpage

161

Lastpage

171

Abstract

Motorola´s MC 145532 ADPCM (adaptive digital pulse-code-modulation) transcoder described is a 16-pin CMOS VLSI application specific digital signal processor (DSP) that implements in full-duplex mode the ANSI (T1.301-1987) standard algorithm for 32-kb/s ADPCM. The application is illustrated of structured test techniques, such as scan path and signature analysis, which are used to enhance the testability of this VLSI signal processor. To perform in real time the numerous computations required by the algorithm, the MC 145532 contains a DSP engine that executes microcode instructions at a 10 MHz rate. The MC145532 was built using 1.5-μm CMOS technology that has double-level metal capability. The size is roughly 145×210 mils with a transistor count of approximately 50 k transistors

Keywords

CMOS integrated circuits; VLSI; automatic testing; digital signal processing chips; integrated circuit testing; pulse-code modulation; real-time systems; 1.5 micron; 10 MHz; 32 kbit/s; ADPCM transcoder; ANSI; CMOS VLSI application specific digital signal processor; DSP engine; MC 145532; Motorola; VLSI signal processor; adaptive digital pulse-code-modulation; double-level metal capability; full-duplex mode; microcode instructions; scan path; signature analysis; structured test; testability; ANSI standards; CMOS process; CMOS technology; Digital signal processing; Digital signal processors; Signal analysis; Signal processing; Signal processing algorithms; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207794

Filename

207794