Title :
Linearity characterization of nano-scale underlap SOI MOSFETs
Author :
Singh, Indra Vijay ; Alam, Md Shamsul
Author_Institution :
Dept. of Electron. Eng., Aligarh Muslim Univ., Aligarh, India
Abstract :
This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer “s”, film thickness “Tsi”and doping gradient “d” to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain Av, IP3, maximum oscillation frequency fMAX and dc power consumption PDC, it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of fMAX, Av and IP3 in DG configuration with power consumption of ~ 2.1 mW. The higher value of FoM in DG device has been achieved at similar “on” to “off” current ratio (Ion/Ioff) as specified in current International Technology Road map for Semiconductors (ITRS).
Keywords :
MOSFET; high-k dielectric thin films; semiconductor doping; silicon-on-insulator; ITRS; International Technology Road map for Semiconductors; Si; dc power consumption; doping gradient; double gate configurations; figure-of-merit; film thickness; high-k stack; intrinsic gain; linearity characterization; nanoscale underlap SOI MOSFET; oscillation frequency; process parameters; silicon-on-insulator; single gate configurations; spacer; third order intercept; Doping; Films; Linearity; Logic gates; MOSFET; Performance evaluation; Radio frequency; Double Gate; Low Power; Non-Linearity; Silicon-on-Insulator; Underlap design;
Conference_Titel :
India Conference (INDICON), 2013 Annual IEEE
Conference_Location :
Mumbai
Print_ISBN :
978-1-4799-2274-1
DOI :
10.1109/INDCON.2013.6726009
