What is the path to fast fault simulation?

Author

Abramovici, Miron ; Krishnamurthy, Balaji ; Mathews, Rob ; Rogers, Bill ; Schulz, Michael ; Seth, Sharad ; Waicukauski, John

Author_Institution

AT&T Inf. Syst., Holmdel, NJ, USA

fYear

1988

fDate

12-14 Sep 1988

Firstpage

183

Lastpage

192

Abstract

Motivated by the advances in fast fault-simulation techniques for large combinational circuits, a panel discussion was organized for the 1988 International Test Conference. A collective account of the position statements is offered by the panelists. The panelists present discussions on the following topics: introduction to fault simulation; parallel pattern fault simulation; intelligent heuristics; graph-theoretic approaches; approximate solutions; hierarchical fault simulation; and hardware solutions

Keywords

automatic testing; combinatorial circuits; digital simulation; fault location; integrated circuit testing; integrated logic circuits; logic testing; approximate solutions; automatic testing; combinational circuits; hierarchical fault simulation; intelligent heuristics; logic testing; parallel pattern fault simulation; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Electrical fault detection; Fault detection; Laboratories; Logic testing; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207796

Filename

207796