Title :
The MSP.RTL real-time scheduler synthesis tool
Author :
Mok, Aloysius K. ; Tsou, Duu-Chung ; de Rooij, R.C.M.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
MSP.RTL is a tool for producing real time schedulers for a wide variety of timing constraints. The input to MSP.RTL can be customized for different application domains, as long as their timing semantics can be expressed in RTL (real time logic). The scheduler synthesis algorithm treats the real time scheduling problem as a temporal constraint satisfaction problem with additional resource constraints. The current version of MSP.RTL computes cyclic schedules for multiprocessor systems in a three part process: the first part constructs a temporal constraint graph representing the input timing specification. The second part finds a set of solutions of the temporal constraint graph by using a combination of constraint satisfaction and an incremental positive cycle detection algorithm. The third part searches the set of solutions to find a feasible schedule which satisfies the resource constraints by exploiting search strategies and results from real time scheduling theory. We have used the MSP.RTL tool to solve same benchmark problems including a sanitized version of the Boeing 777 Integrated Airplane Information Management System (AIMS)
Keywords :
constraint theory; formal logic; processor scheduling; real-time systems; resource allocation; temporal logic; travel industry; AIMS; Boeing 777 Integrated Airplane Information Management System; MSP RTL real time scheduler synthesis tool; application domains; constraint satisfaction; cyclic schedules; feasible schedule; incremental positive cycle detection algorithm; input timing specification; real time logic; real time scheduling problem; real time scheduling theory; resource constraints; scheduler synthesis algorithm; search strategies; temporal constraint graph; temporal constraint satisfaction problem; timing constraints; timing semantics; Detection algorithms; Engines; Informatics; Logic; Mathematics; Multiprocessing systems; Processor scheduling; Runtime; Scheduling algorithm; Timing;
Conference_Titel :
Real-Time Systems Symposium, 1996., 17th IEEE
Conference_Location :
Los Alamitos, CA
Print_ISBN :
0-8186-7689-2
DOI :
10.1109/REAL.1996.563706