Design and implementation of logical cost efficient nanometric fault tolerant reversible BCD adder

Reversible Logic is one of the emerging computational methodology which assures zero power dissipation through theoretical laws of thermodynamics. Fault Tolerance property in reversible logic is achieved by using a special class of reversible logic gates called the parity preserving gates. This paper presents a novel BCD adder which has a distinguished architecture than those prevalent in the literature, constructed using proposed Parity Conserving Toffoli Gate (PCTG) and Double Feynman Gate. The proposed structure has the least logical cost than all the other designs studied under the scope. The reversible logic being the nucleus of nanotechnology, the circuits are at the nanometric scale.