WTPGA: a novel weighted test-pattern generation approach for VLSI built-in self test

Author

Siavoshi, Fardad

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

fYear

1988

fDate

12-14 Sep 1988

Firstpage

256

Lastpage

262

Abstract

A weighted test-pattern generation approach (WTPGA) is reported and applied to two very well known circuits. WTPGA was applied specifically to a 4-bit ALU (arithmetic logic unit) and a minimal set of test patterns with very high fault coverage resulted. It has been observed that there exists a correlation between the rate of the circuit switching activity on application of the test-patterns and the increase in fault coverage. WTPGA also takes advantage of functional test patterns in computation of the signal probabilities and it is known that good functional test sets fully exercise the circuit. It is also implied that the technique described can be applied in developing a minimal set of pseudorandom patterns, generated internal to the device for built-in self-test

Keywords

VLSI; fault location; integrated circuit testing; logic testing; probability; 4 bit; IC testing; VLSI built-in self test; arithmetic logic unit; circuit switching; correlation; fault coverage; logic testing; pseudorandom patterns; signal probabilities; weighted test-pattern generation; Automatic testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Large scale integration; Logic testing; Switching circuits; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207810

Filename

207810