Fault modeling and test algorithm development for static random access memories

Author

Dekker, Rob ; Beenker, Frans ; Thijssen, Loek

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1988

fDate

12-14 Sep 1988

Firstpage

343

Lastpage

352

Abstract

A fault model for SRAMs (static random-access memories) is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) plus a data retention test are proposed that cover 100% of the faults under the fault model. The 13N test algorithm is generally applicable while the 9N algorithm can only be used in SRAMs with combinational R/W logic. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms is verified by a large number of actual wafer tests and device failure analysis

Keywords

automatic testing; integrated circuit testing; integrated memory circuits; random-access storage; IC testing; SRAMs; automatic testing; data retention test; device failure analysis; fault model; linear test algorithms; local disturbances; physical spot defects; static random access memories; wafer tests; Circuit faults; Circuit testing; Decoding; Laboratories; Logic arrays; Logic devices; Logic testing; Mathematical model; Random access memory; SRAM chips;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207820

Filename

207820