A realistic self-test machine for static random access memories

A self-test machine for static random access memories (SRAMs) has been developed. It is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds. The test algorithm implemented has excellent fault-detection capabilities and is extremely regular and symmetric, which results in a minimum of hardware overhead and performance loss. Self-test reduces the possibilities for diagnostic tests. A form of scan test remains necessary in spite of a self-test implementation. This self-test design offers full scan test facilities of both the SRAM and the self-test logic itself. This version of the SRAM self-test is currently being implemented in a number of digital signal processing chips and will, after a final evaluation, be used for a broad scope of designs