DocumentCode
3111145
Title
Dual port static RAM testing
Author
Raposa, Manuel J.
Author_Institution
Sun Microsyst. Inc., Mountain View, CA, USA
fYear
1988
fDate
12-14 Sep 1988
Firstpage
362
Lastpage
368
Abstract
The basics are presented of a test methodology used for dual-port static RAMs (random-access memories). The fundamental problem in testing dual-port static RAMs is how to address the entire array from both sides individually. Any memory tester with dual pattern generators and dual timing systems would suffice, but most existing memory testers were designed and built before dual-port static RAMs were introduced, and offer no such solution. The following three methods have been proposed, and the advantages and disadvantages of each one explored. They are: same address, both ports; complement address; and separation of ports
Keywords
integrated circuit testing; integrated memory circuits; logic testing; random-access storage; IC testing; SRAM; array; complement address; dual pattern generators; dual timing systems; dual-port static RAMs; logic testing; memory tester; separation of ports; Circuit testing; Hardware; Logic arrays; Logic testing; Message passing; Process design; Random access memory; Read-write memory; Sun; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-8186-0870-6
Type
conf
DOI
10.1109/TEST.1988.207822
Filename
207822
Link To Document