A RDT-based interconnection network for scalable network-on-chip designs

The interconnection network plays an important role in the performance and energy consumption of a network-on-chip (NoC) system. In this paper, we propose a RDT(2,2,1)/α-based interconnection network for NoC designs. RDT(2,2,1)/α is constructed by recursively overlaying 2D diagonal meshes (torus). The number of layers needed for routing the links in RDT(2,2,1)/α is shown to be bounded at 6, which is feasible to be implemented with current and future VLSI technologies. With the innovative diagonal structure and its simple rank assignment, RDT(2,2,1)/α possesses the following features: recursive structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8, and robust routing schemes. These features make RDT(2,2,1)/α a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy-efficiency, customizability, and fault-tolerance.