DocumentCode
3111244
Title
Evaluating the limitations of high-speed board testers
Author
Arena, John
Author_Institution
Teradyne Inc., Boston, MA, USA
fYear
1988
fDate
12-14 Sep 1988
Firstpage
411
Lastpage
420
Abstract
The factors which limit both in-circuit and functional test system performance are discussed, and techniques that can be used to minimize their effects are suggested. Two simple models are developed to calculate actual test performance, or to compare different tester models against a hypothetical board design
Keywords
printed circuit testing; functional test system; high-speed board testers; in-circuit testing; models; Clocks; Detectors; Fault detection; Logic testing; Physics; Programming profession; Stress; System performance; System testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-8186-0870-6
Type
conf
DOI
10.1109/TEST.1988.207828
Filename
207828
Link To Document