A BIST design of structured arrays with fault-tolerant layout

Author

Katoozi, Mehdi ; Soma, Mani

Author_Institution

Seattle Silicon Corp., Bellevue, WA, USA

fYear

1988

fDate

12-14 Sep 1988

Firstpage

514

Lastpage

521

Abstract

A BIST (built-in self-test)-compatible method for the design, layout, and test of structured logic arrays is presented. The layout is analyzed for realistic faults in the conducting layers of a typical CMOS process. It is found that only one-third of the faults while occurring as a result of random spot defects are classical stuck faults while others have to be manipulated by the appropriate test vectors to manifest themselves as stuck faults further down in the circuit. Many of these faults are detected by the test method adopted without any special provisions in the circuit. This technique eliminates the need for placing shift registers and exclusive-OR gates on the product lines of the array

Keywords

CMOS integrated circuits; integrated circuit testing; logic arrays; logic design; logic testing; production testing; BIST design; CMOS; IC testing; built-in self-test; conducting layers; fault-tolerant layout; logic design; logic testing; product lines; random spot defects; structured arrays; structured logic arrays; stuck faults; test vectors; Automatic testing; Built-in self-test; CMOS logic circuits; Circuit faults; Circuit testing; Design methodology; Fault tolerance; Logic arrays; Logic design; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207831

Filename

207831