Fault bundling: reducing machine evaluation activity in hierarchical concurrent fault simulation

A method of bundling error data is proposed which should significantly reduce the amount of explicit functional evaluation required for hierarchical concurrent simulation. The bundling operation is carried out at run time, and so is different from but complementary to approaches such as WRAP, which compress unnecessary or uninteresting portions of circuit hierarchy. The technique is exact; it does not cause the simulation to become probabilistic. This work extends the concept of multilist traversal (MLT). A hierarchy is imposed on the conventional machine list which matches the design hierarchy of the circuit under simulation. The resulting improvement in machine-list organization is expected to prevent multiple evaluations of behavioral primitives for collections of faults which present the same input value