Process and device simulations to study the impact of Ge profile of 65 nm NPN SOI HBT with buried layer

Author

Misra, Prasanna Kumar ; Patil, Ganesh C. ; Qureshi, Shaima

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. Kanpur, Kanpur, India

fYear

2013

fDate

13-15 Dec. 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, the npn SOI HBT with buried layer has been studied through process and device simulations for different Ge profile. The simulation results of the HBT are compared with triangular, box and trapezoidal like Ge profiles in the base layer. The tradeoff in the performance of HBT is studied in terms of collector currents, DC current gains, AC voltage gain, unity current gain frequencies and breakdown voltages. From the results it has been observed that the HBT with triangular Ge profile has higher f_tBV_CEO product i.e 447 GHzV. Also the HBT with this profile offers highest voltage gain compared to the other Ge profiles. The peak f_t value of this SOI HBT has been obtained at 2.31 mA of collector current value.

Keywords

buried layers; electric breakdown; elemental semiconductors; germanium; heterojunction bipolar transistors; AC voltage gain; DC current gains; Ge; NPN SOI HBT; breakdown voltages; buried layer; collector currents; device simulations; process simulations; size 65 nm; triangular Ge profile; unity current gain; CMOS integrated circuits; Doping; Heterojunction bipolar transistors; Impact ionization; Impedance; Performance evaluation; Silicon germanium; Buried Layer; SOI; Sentaurus; SiGe HBT;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference (INDICON), 2013 Annual IEEE

Conference_Location

Mumbai

Print_ISBN

978-1-4799-2274-1

Type

conf

DOI

10.1109/INDCON.2013.6726051

Filename

6726051