High-speed VLSI implementation of IIR lattice filters

Merged arithmetic has been used to provide speedup and hardware savings in the implementation of DSP algorithms by utilizing the properties of column compression multipliers and merging multiple multiply-accumulates into one circuit block. A use of partially merged arithmetic was previously demonstrated in the design of FIR lattice filters which partially combined the multiply accumulate functions of adjacent lattice filter stages while still retaining the basic properties of lattice filters; modularity, good quantization characteristics, and the direct use of reflection coefficients. The same techniques are applied to IIR lattice filters.