Adaptive compensation of analog circuit imperfections for cascaded /spl Sigma//spl Delta/ modulators

Multi-bit cascaded sigma-delta (SD) modulators are known to suffer from performance degradation caused by analog circuit imperfections. A method is introduced for the adaptive digital on-line compensation of linear errors, such as finite op-amp gain and capacitor mismatch. The method is discussed by considering a two-stage 3rd-order multi-bit switched-capacitor modulator. It uses a square-wave dither signal in the first stage as a test signal, and minimizes the power of its fundamental harmonic in the output signal. Extensive behavioral simulations show that nearly perfect compensation can be achieved with only slightly increased hardware complexity.