Threading a multiple scan paths in a VLSI circuit

Author

Bhawmick, S. ; Khaira, M.S. ; Mishra, P.P. ; Das, A. ; Dasgupta, A. ; Palchaudhury, P.

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

fYear

1988

fDate

12-14 Sep 1988

Firstpage

735

Lastpage

743

Abstract

The problem of configurating multiple scan paths in a VLSI circuit is discussed. Based on the analysis of the circuit, certain specific subcircuits are identified and a scan path is next configured for testing each such subcircuit. Rather than the algorithmic approach, a knowledge-based system strategy has been adopted to automate the approach taken by a human designer to tackle the problem

Keywords

VLSI; automatic testing; circuit CAD; integrated circuit testing; knowledge based systems; CAD; IC testing; VLSI circuit; knowledge-based system; multiple scan paths; subcircuits; Algorithm design and analysis; Circuit testing; Integrated circuit interconnections; Latches; Logic circuits; Logic testing; Pins; Programmable logic arrays; Registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207859

Filename

207859

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3111890