Integration of algorithmic VLSI synthesis with testability incorporation

A design synthesis methodology is presented with testability, area, and delay constraints applied throughout the design search. In general, the methodology differs from other synthesis approaches by implementing testability as part of the VLSI design solution. A binary-tree data structure is used for testable design synthesis, with bottom-up and top-down tree algorithms. Results show the best test methodologies for different design solutions of the same functionality will vary and the best testable design solution is not always the same as that obtained from using only area and delay as search constraints