Timing generation for DSP testing

DSP-based testing places constraints on the timing generation system of a mixed signal tester. These constraints are in addition to the constraints placed by the digital subsystem. These requirements are studied and a test system architecture that meets these needs is proposed. When using coherent test techniques to perform undersampling in a system that uses a single master clock, effective sampling frequencies are limited to the highest frequency of the master clock. The author explores the impact of this limitation. An alternate architecture for establishing coherent test conditions is presented. How this architecture effectively removes the constraints associated with a single master clock is shown