DocumentCode :
3112
Title :
On-Chip Active Messages for Speed, Scalability, and Efficiency
Author :
Harting, R. Curtis ; Dally, William J.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Volume :
26
Issue :
2
fYear :
2015
fDate :
Feb. 2015
Firstpage :
507
Lastpage :
515
Abstract :
This paper describes and quantifies the benefits of adding low-overhead active messages to many-core, cache-coherent chip-multiprocessors. The active messages we analyze are user defined and trigger the atomic execution of a custom software handler at the destination. Programmers can use these active messages to both move data with less overhead than cache coherency and, more importantly, explicitly send computation to data. Doing so greatly improves (11× speed, 4.8× energy) communication idioms such as shared object modification, reductions, data walks, point-to-point communication, and all-to-all communication. Active messages enhance program scalability: applications using them run 63 percent faster with 11 percent less energy on 256 cores. The relative benefits of active messages grow with larger numbers of cores.
Keywords :
cache storage; microprocessor chips; multiprocessing systems; atomic execution; cache coherent chip multiprocessors; communication idioms; many core; onchip active messages; program scalability; Hardware; Message systems; Program processors; Programming; Registers; Scalability; MIMD processors; Parallel architecture; concurrent programming; parallel processors; shared memory;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/TPDS.2014.2307874
Filename :
6747410
Link To Document :
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