Boolean decomposition of programmable logic arrays

The authors present algorithms for Boolean decomposition, which decompose a two-level logic function into a cascade of smaller two-level logic functions, such that the overall area of the resulting logic network is minimized. The algorithms are based on multiple-valued minimization. Given a PLA (programmable logic array), a subset of inputs to the PLA is selected. This selection step incorporates a novel algorithm which selects a set of inputs such that the cardinality of the multiple-valued cover, produced by representing all combinations of these inputs as different values of a single multiple-valued variable, is much smaller than the original binary cover cardinality. A relatively small size for the multiple-valued cover implies that the number of good Boolean factors contained in this subset of inputs are re-encoded to satisfy the constraints given in the multiple-valued cover, thus producing a binary cover for the original PLA whose cardinality equals the multiple-valued cover cardinality