Title :
TOBOL-a new methodology for the top-to-bottom level hardware description in VLSI design-automation systems
Author :
Chen, C. Y Roger
Author_Institution :
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Abstract :
The TOBOL methodology for hardware description from top to bottom level is proposed. Multilevel circuit descriptions can efficiently be provided for diversified purposes. Low-level (such as transistor-level) design information can easily be attached into high-level descriptions. TOBOL utilizes consistent data representations at different levels and allows the integration of circuit descriptions at different levels into a single unified system. Therefore, redundant information is greatly reduced, and efficient access of right functional abstractions of circuits is achieved
Keywords :
VLSI; circuit layout CAD; specification languages; TOBOL; VLSI; circuit descriptions; circuit layout CAD; data representations; design-automation; functional abstractions; high-level descriptions; specification languages; top-to-bottom level hardware description; Circuit synthesis; Computer languages; Data structures; Design automation; Hardware; Logic circuits; Logic design; Microelectronics; Process design; Very large scale integration;
Conference_Titel :
Computer Languages, 1988. Proceedings., International Conference on
Conference_Location :
Miami Beach, FL
Print_ISBN :
0-8186-0874-9
DOI :
10.1109/ICCL.1988.13090