DocumentCode :
3112276
Title :
Microstructure and electrical properties of Ge- and Si-nanoclusters in implanted gate oxide for embedded memory applications
Author :
Stegemann, K.-H. ; Thees, H.-J. ; Wittmaack, M. ; Borany, J.V. ; Heeinig, K.H. ; Gebel, T.
Author_Institution :
Zentrum Mikroelektronik Dresden, Germany
fYear :
2000
fDate :
2000
Firstpage :
32
Lastpage :
37
Abstract :
MOSFETs with gate oxides containing nanoclusters (Si,Ge) fabricated with different techniques (implantation, LPCVD, sputtering) are a very promising approach for future memories. This contribution reports on results obtained on Si- or Ge-implanted MOS capacitors and transistors. By varying the implantation and annealing parameters the Si or Ge depth profile and the cluster size and distribution can be controlled. The experimental results are explained by a theoretical model, which is based on TRIM calculations, rate-equation studies and 3D kinetic Monte Carlo simulations. The electrical properties of gate-SiO 2 containing Si- or Ge-nanoclusters are investigated in detail with emphasis on its feasibility for embedded memories for system on chip applications
Keywords :
EPROM; MOS capacitors; MOSFET; Monte Carlo methods; annealing; doping profiles; germanium; ion implantation; nanotechnology; silicon; silicon compounds; 3D kinetic Monte Carlo simulations; MOS capacitors; MOSFET; SiO2:Ge; SiO2:Si; TRIM calculations; annealing; cluster distribution; cluster size; depth profile; embedded memory; implanted gate oxide; ion implantation; nanoclusters; rate-equation; system on chip applications; Annealing; CMOS process; MOS capacitors; MOSFETs; Microstructure; Semiconductor films; Size control; Sputtering; System-on-a-chip; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ion Implantation Technology, 2000. Conference on
Conference_Location :
Alpbach
Print_ISBN :
0-7803-6462-7
Type :
conf
DOI :
10.1109/.2000.924083
Filename :
924083
Link To Document :
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