Optimization of n-junction through ion beam shadowing and buffering effect by tilt implantation with rotation for improving the retention time

The novel junction process scheme in submicron DRAM cell with STI (Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ΔRP (projected standard deviation) increase using buffered N-implantation with tilt and 4×(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component[1]. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is intentionally caused by Ion Beam Shadowing and Buffering Effect using tilt implantation with 4×-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and N_d/N_a ratio