Technical and economic considerations for retrograde well and channel implants

We compare batch high energy to serial medium current implanters for an advanced CMOS process containing multiple modulated well implant steps. Both device performance and implant costs were examined. We modeled the effect of ion beam angle variations in batch endstations in TCAD using a silicon calibrated 0.18 μm CMOS process, investigating three different sized transistors (0.18, 0.15 and 0.13 μm). No significant difference in either the NMOS or PMOS transistors can be observed. Cost modeling for a multiple modulated well process indicate that from a fab level perspective, batch high energy implanters have a lower total capital cost, footprint, and cost per wafer out than serial medium current implanters, because the higher throughput of the batch implanters means fewer are required. Finally, we show model results indicating that the use of quad implants for retrograde wells improves isolation robustness for narrow STI structures as compared to asymmetric implants