Designing state machines for testability

The current generation of programmable logic devices provides circuit designers with options in high-speed controller design. These devices fill the performance gap between low-cost integrated microcontrollers and more expensive ASIC (application-specific) solutions. A technique of designing state machines that are easily testable is described. The design technique presented utilizes characteristics of these devices to provide testability with little or no design overhead. The background and motivation for this technique is described and its use is demonstrated both in general and with practical design examples