• DocumentCode
    3112860
  • Title

    High-level synthesis and optimization strategies in Hercules and Hebe

  • Author

    Ku, David ; De Micheli, Giovanni

  • Author_Institution
    Center for Integrated Syst., Stanford Univ., CA, USA
  • fYear
    1990
  • fDate
    29 May-1 Jun 1990
  • Firstpage
    124
  • Lastpage
    129
  • Abstract
    Presents an approach to automated synthesis of digital circuits from behavioral specifications. The system, called Hercules and Hebe, offers many advantages to the designer. First, the system supports constraint-driven synthesis where timing and resource constraints are applied to guide the synthesis decisions. Second, systematic design space exploration is possible, where the designer explores the tradeoff between area and performance to meet the design objectives. Third, logic synthesis techniques are uniformly incorporated within the synthesis framework to provide estimates to guide high-level decisions. Along with a synthesis oriented hardware description language called HardwareC, Hercules/Hebe provides an environment for the design of general synchronous digital circuits, with specific attention to the requirements of ASIC designs. The system has been applied to complex ASIC designs, including the Digital Audio I/O, MAMA, and Bi-Dimensional DCT chips
  • Keywords
    VLSI; circuit layout CAD; digital integrated circuits; specification languages; ASIC designs; Bi-Dimensional DCT chips; Digital Audio I/O; HDL; HardwareC; Hebe; Hercules; MAMA; automated synthesis of digital circuits; behavioral specifications; constraint-driven synthesis; high-level optimisation strategies; high-level synthesis strategies; logic synthesis techniques; resource constraints; synchronous digital circuits; synthesis oriented hardware description language; systematic design space exploration; tradeoff between area and performance; Application specific integrated circuits; Circuit simulation; Circuit synthesis; Digital circuits; Hardware design languages; High level synthesis; Integrated circuit synthesis; Logic; Signal synthesis; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Euro ASIC '90
  • Conference_Location
    Paris
  • Print_ISBN
    0-8186-2066-8
  • Type

    conf

  • DOI
    10.1109/EASIC.1990.207906
  • Filename
    207906