Title :
Improved yield model for submicron domain
Author :
Pleskacz, Witold A. ; Maly, Wojciech
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
This paper describes a new manufacturing yield model for submicron VLSI circuits. This model attempts to handle process induced differences between IC layout and actual IC topography. The presented model focuses on the random nature of over and under etching phenomenon. The relevance of the new yield model in submicron domain is analyzed. Examples of yield calculations using the proposed model are presented as well
Keywords :
VLSI; etching; integrated circuit layout; integrated circuit yield; semiconductor process modelling; IC layout; IC topography; VLSI; manufacturing yield model; over etching phenomenon; process induced differences; submicron domain; under etching phenomenon; Computer aided manufacturing; Conducting materials; Etching; Integrated circuit layout; Integrated circuit modeling; Modems; Pulp manufacturing; Surfaces; Very large scale integration; Virtual manufacturing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
0-8186-8168-3
DOI :
10.1109/DFTVS.1997.628303
