A pipelined/interleaved IIR digital filter architecture

By using a clock rate that is K times the data rate and with interleaved feedback of the output samples, a single expanded digital filter H(z^K) can be made equivalent to a cascade of k identical filters H^k(z) with 1⩽k⩽K. Whereas this novel pipelining/interleaving (PT) technique can equally be employed for implementing high-performance FIR filters, its main benefit lies in that more efficient high-speed IIR filters become achievable, though their highest possible data rates are still limited by the delays of the critical feedback loops. Hardware architectures and design examples with K=2 are presented to show how the PI technique works for implementing high-speed IIR filters made as the sum of two allpass functions