Application of a yield model merging critical areas and defectivity to industrial products

Author

Levasseur, Sandra ; Duvivier, Frederic

Author_Institution

Central R&D, SGS-Thomson Microelectron., Crolles, France

fYear

1997

fDate

20-22 Oct 1997

Firstpage

11

Lastpage

19

Abstract

This paper reports a yield model merging critical areas computed by a survey sampling based estimation tool (EYES) and a large set of defectivity measurements performed during the fabrication process at the SGS-Thomson Crolles plant. This model is applied to commercial devices processed in a mature 0.5 μ technology. The robustness of the model was tested with a large number of lots including multiple products, process versions (routes) and defectivity variations

Keywords

VLSI; digital simulation; integrated circuit yield; semiconductor process modelling; 0.5 micron; EYES; SGS-Thomson Crolles plant; critical areas; defectivity; fabrication process; industrial products; multiple products; process versions; robustness; survey sampling based estimation tool; yield model; Circuit faults; Eyes; Integrated circuit modeling; Integrated circuit yield; Merging; Pollution measurement; Predictive models; Sampling methods; Semiconductor device manufacture; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on

Conference_Location

Paris

ISSN

1550-5774

Print_ISBN

0-8186-8168-3

Type

conf

DOI

10.1109/DFTVS.1997.628304

Filename

628304