Title :
Multi-level synthesis on programmable devices in the ASYL system
Author :
Saucier, Gabrielle ; Sicard, Pascal ; Bouchet, Laurent
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
fDate :
29 May-1 Jun 1990
Abstract :
Starting from Boolean equations or, at a higher level, from a control flowchart, the automatic synthesis tool presented here, looks for an optimized mapping on a network of programmable modules. For PALs, the output will be a network of PALs and a netlist ready for a Jedec fusemap; for the Xilinx PGAs the system delivers a network of Xilinx blocks and a netlist. For the last target a place and route phase is necessary
Keywords :
Boolean functions; logic CAD; logic arrays; ASYL system; Boolean equations; CAD; Jedec fusemap; PAL; PLA; Xilinx PGAs; automatic synthesis tool; control flowchart; multilevel synthesis; netlist; optimized mapping; place/route phase; programmable devices; Automatic control; Boolean functions; Control system synthesis; Electronics packaging; Equations; Flowcharts; Kernel; Minimization; Network synthesis; Programmable logic arrays;
Conference_Titel :
Euro ASIC '90
Conference_Location :
Paris
Print_ISBN :
0-8186-2066-8
DOI :
10.1109/EASIC.1990.207924
