DocumentCode
3113393
Title
Vantage Spreadsheet-a new approach to VHDL simulation
Author
Page, Ale F.
Author_Institution
Vantage Anal. Syst., Fremont, CA, USA
fYear
1990
fDate
29 May-1 Jun 1990
Firstpage
181
Lastpage
186
Abstract
The author describes Vantage Spreadsheet, a simulation environment specifically designed for use with VHDL (VHSIC hardware description language). The basic constructs of the language are described, together with the method by which they are integrated into the simulation environment. Further descriptions of particular features of the product are given, including real time schematic simulation
Keywords
circuit analysis computing; digital simulation; specification languages; spreadsheet programs; VHDL simulation; VHSIC; Vantage Spreadsheet; hardware description language; real time schematic simulation; simulation environment; Analytical models; Bibliographies; Contracts; Electronics industry; Hardware design languages; Industrial electronics; Integrated circuit interconnections; Process design; Switches; Very high speed integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '90
Conference_Location
Paris
Print_ISBN
0-8186-2066-8
Type
conf
DOI
10.1109/EASIC.1990.207935
Filename
207935
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