DocumentCode
3113451
Title
An ASIC controller for the TMS 320, 2-generation digital signal processor
Author
Creanza, G. ; Ventrella, O. ; Colangeli, G. ; Subiaco, E.
Author_Institution
Tecnopolis Casta, Valenzano, Italy
fYear
1990
fDate
29 May-1 Jun 1990
Firstpage
197
Lastpage
200
Abstract
The authors deal with an ASIC that integrates all the glue logic that allows one or more DSPs, organized in a multiprocessor, linear array system, to communicate with their memories, with a host processor and among themselves. This circuit has been developed as a gate array in the ALCATEL FACE research center with the collaboration of TECNOPOLIS CSATA
Keywords
application specific integrated circuits; digital signal processing chips; logic arrays; multiprocessing systems; storage management chips; ASIC controller; DSP; TMS 320; digital signal processor; gate array; glue logic; linear array system; memory communication; multiprocessor; Application specific integrated circuits; Decoding; Digital signal processing; Digital signal processors; EPROM; Logic arrays; Logic circuits; Random access memory; Read-write memory; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '90
Conference_Location
Paris
Print_ISBN
0-8186-2066-8
Type
conf
DOI
10.1109/EASIC.1990.207939
Filename
207939
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