DocumentCode
3113554
Title
A neuron processor for neural networks on silicon
Author
Ouali, Jamel ; Saucier, Gabrihle
Author_Institution
Inst. Nat. Polytech. de Grenoble/CSI, France
fYear
1990
fDate
29 May-1 Jun 1990
Firstpage
232
Lastpage
235
Abstract
A neuron processor has been designed and implemented on silicon in a 1.5 μm CMOS technology. It implements a relaxation algorithm with 8 bits precision for the state and the coefficients, and a sigmoidal activation function. It is the building block of a distributed synchronous architecture in which data circulate through shifting techniques
Keywords
CMOS integrated circuits; elemental semiconductors; microprocessor chips; neural nets; parallel architectures; silicon; 1.5 micron; CMOS technology; Si; distributed synchronous architecture; neural networks; neuron processor; relaxation algorithm; shifting techniques; sigmoidal activation function; CMOS process; CMOS technology; Computer architecture; Concurrent computing; Information processing; Neural networks; Neurons; Process design; Silicon; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '90
Conference_Location
Paris
Print_ISBN
0-8186-2066-8
Type
conf
DOI
10.1109/EASIC.1990.207945
Filename
207945
Link To Document