Title :
Analysis of defect to yield correlation on memories: method, algorithms and limits
Author :
Bichebois, Pascal ; Mathery, Pierre
Author_Institution :
SGS-Thomson Microelectron., Crolles, France
Abstract :
Memory circuits are excellent vehicles for yield enhancement of a process technology for VLSI products. A method was developed which consists of correlating the physical defects detected by in-line inspections with the electrical failures. In this method, two types of errors can affect results. A model is proposed in order to estimate and minimize the number of errors. The defect-yield correlation on memories indicates the priority problems responsible for yield loss. Nevertheless, the contribution of the killer defects detected by in-line inspections to yield loss has to be verified. New algorithms are proposed to provide this data that is often missing in yield management systems
Keywords :
VLSI; failure analysis; inspection; integrated circuit yield; integrated memory circuits; VLSI products; defect to yield correlation; electrical failures; in-line inspections; killer defects; memory circuits; process technology; yield enhancement; yield loss; Algorithm design and analysis; Automatic optical inspection; Circuits; Electron optics; Optical feedback; Optical microscopy; Random access memory; Testing; Vehicles; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
0-8186-8168-3
DOI :
10.1109/DFTVS.1997.628308
