Title :
A parallel processor ASIC for real time pattern recognition
Author :
Mostafavi, M. Taghi ; Vishin, Sanjay ; Dettloff, Wayne D.
fDate :
29 May-1 Jun 1990
Abstract :
A real time pattern processing ASIC is described. By exploiting a 1 u, 3.3 V DLM CMOS technology, a 10 MHz 250 k transistor chip was designed for machine vision applications requiring recognition of objects in real time. The architecture, design, simulation methodology, and test strategy of the chip is discussed
Keywords :
CMOS integrated circuits; application specific integrated circuits; computer vision; computerised pattern recognition; digital signal processing chips; 1 micron; 3.3 V; DLM CMOS technology; machine vision applications; parallel processor ASIC; real time pattern recognition; simulation methodology; test strategy; Application software; Application specific integrated circuits; Bandwidth; CMOS technology; Computer architecture; Image analysis; Image processing; Machine vision; Pattern recognition; Very large scale integration;
Conference_Titel :
Euro ASIC '90
Conference_Location :
Paris
Print_ISBN :
0-8186-2066-8
DOI :
10.1109/EASIC.1990.207959
