DocumentCode
3113908
Title
Built-in self-test for generated blocks in an ASIC environment
Author
Bruchner, Wolfgang ; Achuetz, A.
Author_Institution
European Silicon Structures, Munich, Germany
fYear
1990
fDate
29 May-1 Jun 1990
Firstpage
320
Lastpage
325
Abstract
Techniques for Built-in Self-Test of RAMs embedded within ASIC´s are presented. The test algorithm (sequence) has been laid out with emphasis on high fault coverage and low silicon overhead. It supports existing RAM generator tool and allows for generating a wide spectrum of possible configurations. The BIST circuit itself is a soft-macro built from standard library elements. The schematic will be generated automatically on design station according to user specifications. User friendliness was a top goal for the development
Keywords
application specific integrated circuits; built-in self test; integrated circuit testing; random-access storage; ASIC environment; BIST; Built-in Self-Test; RAMs; design station; fault coverage; silicon overhead; soft-macro; standard library elements; test algorithm; user specifications; Application specific integrated circuits; Built-in self-test; Circuit faults; Coupling circuits; Decoding; Geometry; Process control; Random access memory; Read-write memory; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '90
Conference_Location
Paris
Print_ISBN
0-8186-2066-8
Type
conf
DOI
10.1109/EASIC.1990.207962
Filename
207962
Link To Document