Generation and verification of tests for analogue circuits subject to process parameter deviations

Author

Spinks, S.J. ; Chalk, C.D. ; Bel, I.M. ; Zwolinski, M.

Author_Institution

Dept. of Electron. Eng., Hull Univ., UK

fYear

1997

fDate

20-22 Oct 1997

Firstpage

100

Lastpage

108

Abstract

The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower

Keywords

analogue integrated circuits; analogue multipliers; automatic testing; integrated circuit testing; RMS AC supply current monitoring; analogue multiplier circuit; catastrophic fault detection; detection probability metric; fault coverage; fault masking; fault simulation; process parameter deviations; test pattern generation; verification; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Current supplies; Electrical fault detection; Fault detection; Manufacturing processes; Predictive models; Sensitivity analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on

Conference_Location

Paris

ISSN

1550-5774

Print_ISBN

0-8186-8168-3

Type

conf

DOI

10.1109/DFTVS.1997.628315

Filename

628315