Definition of timing models for compiler-driven logic simulation

The Munich Simulation Engine accelerates compiler-driven simulation and is able to exploit a design´s parallelism without restrictions. Advocates of table-driven simulation-engines, however, claim that concerning timing simulation the advantage of compiler-driven simulation engines only exists for zero-delay and, maybe, unit-delay simulation. Based on experience with an operational model of the Munich Simulation Computer, it is shown how to define all types of timing models for compilers-driven simulation and to discuss how far the performance potential of the Munich Simulation Computer is affected when timing models are coded and executed by means of event-flow graphs