High performance VLSI implementation of CAVLC decoder of H.264/AVC for HD transmission

Context-based Adaptive Variable Length Coding (CAVLC) has been adopted by the latest video coding standard H.264 as one of its entropy encoding techniques. In this paper, VLSI architecture for implementing CAVLC decoder is proposed. The proposed architecture takes into consideration the bit-rate requirements of H.264 without compromising the area. When implemented in Xilinx 10.1i, Virtex-4 technology, the proposed architecture can process frames of HD-1080 format at 30 frames per second working at a frequency of 45 MHz.