DocumentCode
3114054
Title
An experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application
Author
Furuyama, Tohru ; Ohsawa, Takashi ; Nagahama, Yousei ; Tanaka, Hiroto ; Watanabe, Yohji ; Kimura, Tohru ; Muraoka, Kazuyoshi ; Natori, Kenji
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1988
fDate
16-19 May 1988
Abstract
A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application
Keywords
cellular arrays; integrated memory circuits; random-access storage; 2-bit/cell storage technique; DRAM; access time; cell-array area; defect-sensitive; macro cell; memory-on-logic application; yield; Application specific integrated circuits; Data conversion; Equivalent circuits; Large scale integration; Logic circuits; Microcomputers; Random access memory; Read-write memory; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20797
Filename
20797
Link To Document