• DocumentCode
    3114231
  • Title

    Integrated circuit performance optimization with simulated annealing algorithm and SPICE-PAC circuit simulator

  • Author

    Durbin, F. ; Haussy, J. ; Berthia, G. ; Siarry, P. ; Zuberek, W.M.

  • Author_Institution
    CEA Service Electron., Bruyeres-le-Chatel, France
  • fYear
    1990
  • fDate
    29 May-1 Jun 1990
  • Firstpage
    407
  • Lastpage
    412
  • Abstract
    The circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistor geometries . . .) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient rise times, etc.). This task is equivalent to a multidimensional and/or multi objective optimization problem: n-variables functions have to be minimized in an hyperrectangular domain: equality and/or inequality constraints can be eventually specified. The authors propose an efficient algorithm, based on the repeated application of simulated annealing to a certain number of p-variables sub problems, with p≪n. Objective functions are computed through the modular SPICE-PAC simulator, which is controlled by the optimization algorithm
  • Keywords
    circuit CAD; digital simulation; simulated annealing; SPICE-PAC circuit simulator; equality constraints; hyperrectangular domain; inequality constraints; multi objective optimization problem; n-variables functions; operational criteria; optimization algorithm; p-variables sub problems; parameter values; performance optimization; simulated annealing algorithm; Bandwidth; Capacitors; Circuit simulation; Circuit synthesis; Computational geometry; Computational modeling; Constraint optimization; Multidimensional systems; Resistors; Simulated annealing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Euro ASIC '90
  • Conference_Location
    Paris
  • Print_ISBN
    0-8186-2066-8
  • Type

    conf

  • DOI
    10.1109/EASIC.1990.207978
  • Filename
    207978