An efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms

Author

Zhang, Xiao-Dong ; Tsui, Chi-ying

Author_Institution

Dept. of EE, Univ. of Sci. & Technol. of China, Hefei, China

Volume

1

fYear

1997

fDate

21-24 Apr 1997

Firstpage

603

Abstract

This paper describes a VLSI architecture which can be reconfigured to support both Full Search Block-Matching algorithm and 3-step Hierarchical Search Block-Matching algorithm. By using a reconfigurable register-mux array and a parameterizable adder tree, the 2-D array architecture provides efficient real time motion estimation for many video applications. We also propose a memory architecture and an associated switching network to solve the simultaneous data access problem

Keywords

image matching; memory architecture; motion estimation; reconfigurable architectures; VLSI architecture; adder tree; block matching; memory architecture; motion estimation; real time; reconfigurable VLSI architecture; reconfigurable register-mux array; switching network; Adders; Delay; Energy consumption; Memory architecture; Motion estimation; Network-on-a-chip; Systolic arrays; Throughput; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on

Conference_Location

Munich

ISSN

1520-6149

Print_ISBN

0-8186-7919-0

Type

conf

DOI

10.1109/ICASSP.1997.599840

Filename

599840