Verifying ASICs by symbolic simulation

Author

Schmid, Richard ; Tiden, Erik

Author_Institution

Siemens AG, Res. Labs. for Appl. Comput. Sci. & Software, Munich, Germany

fYear

1990

fDate

29 May-1 Jun 1990

Firstpage

468

Lastpage

473

Abstract

A new tool which is capable of dealing with digital circuit designs on a functional, or behavioural, level is presented. The tool has been used extensively in a design center for ASICS, and several real-life applications of it are described. The basis of the new tool is formed by efficient algorithms for manipulating Boolean functions and finite-state machines. Among the applications of the tool are automatic formal verification of combinatorial and sequential circuits, reverse engineering, (e.g. generation of state transition tables from circuit designs), rapid prototyping. validation of new CAD tools, verification of hand optimizations of tool-generated circuits and algorithm design

Keywords

application specific integrated circuits; circuit CAD; combinatorial circuits; logic CAD; logic arrays; sequential circuits; software tools; ASICs; Boolean functions; CAD tools; algorithm design; automatic formal verification; combinatorial circuits; digital circuit designs; finite-state machines; rapid prototyping; reverse engineering; sequential circuits; state transition tables; symbolic simulation; Application specific integrated circuits; Boolean functions; Circuit simulation; Circuit synthesis; Design automation; Digital circuits; Formal verification; Prototypes; Reverse engineering; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '90

Conference_Location

Paris

Print_ISBN

0-8186-2066-8

Type

conf

DOI

10.1109/EASIC.1990.207990

Filename

207990